Dual Loop PLL for a Radio Frequency Transceiver

In this paper, a high frequency dual PLL for a radio frequency transceiver is proposed. This new PLL architecture, which relaxes the trade off design constrains, consists in two PLL loops that drive the same VCO. The first loop has a high current charge pump that drives the high gain VCO side and is aimed to improve the settling time performance. The second loop has a low current charge pump that drives the low gain VCO side in order to obtain a good phase noise performance. The simulations results show that this architecture has better performances than a single loop PLL.